Over on Hackaday, we've seen that Anders Nielsen gave a talk at Hackaday Europe 2026 about his effort to build a software-defined radio with 20 MHz of bandwidth on a bill of materials of under US$50. We've posted about his work before, first with the PhaseLoom quadrature sampling front end, and later with PhaseLatch, which combined a 20 MSPS ADC with a 50-year-old MOS 6502 CPU. In this latest work, the 6502 is still part of the stack, but for the wideband work the samples bypass it entirely.

The RF side is a discrete Tayloe detector built around a TLV3253 analog switch, sampling the signal four times per local oscillator cycle to give downconversion and quadrature in one step. A Si5351 provides two clocks offset by 90 degrees from the same PLL, an ADA4891 op amp buffers into a HT9201 dual 20 MHz 10-bit ADC, and an FX2LP clone streams the parallel data over USB 2.0, avoiding the cost and tool chain of an FPGA. USB bandwidth forces a choice between 20 MHz at 8 bits or 10 MHz at 10 bits, and he notes that PCB design was critical in getting a flat frequency response.

Anders ran a live demo streaming 19.375 MHz into GQRX and showing the whole FM band at once, with tuning handled by firmware running on the FX2LP's own 8051 core. Still to come are bias and offset calibration to suppress the mirror images, better filtering and layout, and a front-end mixer to get past the roughly 100 MHz ceiling of the Si5351. He is also looking for help with the SoapySDR driver, so take a look at his GitHub if you have the skills.

Below, we're also embedding the video from his YouTube channel, which covers the same project.